#ifndef	__SPI_H__
#define	__SPI_H__



///* ----------------------------------------------------------------------------
//   -- SPI
//   ---------------------------------------------------------------------------- */
//
///**
// * @addtogroup SPI_Peripheral SPI
// * @{
// */
//
///** SPI - Peripheral register structure */
////typedef struct SPI_MemMap {
////  unsigned long MCR;                                    /**< DSPI Module Configuration Register, offset: 0x0 */
////  unsigned char RESERVED_0[4];
////  unsigned long TCR;                                    /**< DSPI Transfer Count Register, offset: 0x8 */
////#if defined(rvmdk)
////  union {                                          /* offset: 0xC */
////    unsigned long CTAR[2];                                /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
////    unsigned long CTAR_SLAVE[1];                          /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
////  }ct;
////#else
////  union {                                          /* offset: 0xC */
////    unsigned long CTAR[2];                                /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
////    unsigned long CTAR_SLAVE[1];                          /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
////  };
////#endif
////  unsigned char RESERVED_1[24];
////  unsigned long SR;                                     /**< DSPI Status Register, offset: 0x2C */
////  unsigned long RSER;                                   /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
////#if defined(rvmdk)
////  union {                                          /* offset: 0x34 */
////    unsigned long PUSHR;                                  /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
////    unsigned long PUSHR_SLAVE;                            /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
////  }ps;
////#else
////  union {                                          /* offset: 0x34 */
////    unsigned long PUSHR;                                  /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
////    unsigned long PUSHR_SLAVE;                            /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
////  };
////#endif
////  unsigned long POPR;                                   /**< DSPI POP RX FIFO Register, offset: 0x38 */
////  unsigned long TXFR0;                                  /**< DSPI Transmit FIFO Registers, offset: 0x3C */
////  unsigned long TXFR1;                                  /**< DSPI Transmit FIFO Registers, offset: 0x40 */
////  unsigned long TXFR2;                                  /**< DSPI Transmit FIFO Registers, offset: 0x44 */
////  unsigned long TXFR3;                                  /**< DSPI Transmit FIFO Registers, offset: 0x48 */
////  unsigned char RESERVED_2[48];
////  unsigned long RXFR0;                                  /**< DSPI Receive FIFO Registers, offset: 0x7C */
////  unsigned long RXFR1;                                  /**< DSPI Receive FIFO Registers, offset: 0x80 */
////  unsigned long RXFR2;                                  /**< DSPI Receive FIFO Registers, offset: 0x84 */
////  unsigned long RXFR3;                                  /**< DSPI Receive FIFO Registers, offset: 0x88 */
////} volatile *SPI_MemMapPtr;
//
///* ----------------------------------------------------------------------------
//   -- SPI - Register accessor macros
//   ---------------------------------------------------------------------------- */
//
///**
// * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
// * @{
// */
//
//
///* SPI - Register accessors */
//#define SPI_MCR_REG(base)                        ((base)->MCR)
//#define SPI_TCR_REG(base)                        ((base)->TCR)
//#if defined(rvmdk)
//#define SPI_CTAR_REG(base,index2)                ((base)->ct.CTAR[index2])
//#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->ct.CTAR_SLAVE[index2])
//#else	  
//#define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
//#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
//#endif
//#define SPI_SR_REG(base)                         ((base)->SR)
//#define SPI_RSER_REG(base)                       ((base)->RSER)
//#if defined(rvmdk)
//#define SPI_PUSHR_REG(base)                      ((base)->ps.PUSHR)
//#define SPI_PUSHR_SLAVE_REG(base)                ((base)->ps.PUSHR_SLAVE)
//#else		  
//#define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
//#define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
//#endif
//#define SPI_POPR_REG(base)                       ((base)->POPR)
//#define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
//#define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
//#define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
//#define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
//#define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
//#define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
//#define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
//#define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
//
///**
// * @}
// */ /* end of group SPI_Register_Accessor_Macros */
//
//
///* ----------------------------------------------------------------------------
//   -- SPI Register Masks
//   ---------------------------------------------------------------------------- */
//
///**
// * @addtogroup SPI_Register_Masks SPI Register Masks
// * @{
// */
//
///* MCR Bit Fields */
//#define SPI_MCR_HALT_MASK                        0x1u
//#define SPI_MCR_HALT_SHIFT                       0
//#define SPI_MCR_SMPL_PT_MASK                     0x300u
//#define SPI_MCR_SMPL_PT_SHIFT                    8
////#define SPI_MCR_SMPL_PT(x)                       (((unsigned long)(((unsigned long)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
//#define SPI_MCR_CLR_RXF_MASK                     0x400u
//#define SPI_MCR_CLR_RXF_SHIFT                    10
//#define SPI_MCR_CLR_TXF_MASK                     0x800u
//#define SPI_MCR_CLR_TXF_SHIFT                    11
//#define SPI_MCR_DIS_RXF_MASK                     0x1000u
//#define SPI_MCR_DIS_RXF_SHIFT                    12
//#define SPI_MCR_DIS_TXF_MASK                     0x2000u
//#define SPI_MCR_DIS_TXF_SHIFT                    13
//#define SPI_MCR_MDIS_MASK                        0x4000u
//#define SPI_MCR_MDIS_SHIFT                       14
//#define SPI_MCR_DOZE_MASK                        0x8000u
//#define SPI_MCR_DOZE_SHIFT                       15
//#define SPI_MCR_PCSIS_MASK                       0x3F0000u
//#define SPI_MCR_PCSIS_SHIFT                      16
////#define SPI_MCR_PCSIS(x)                         (((unsigned long)(((unsigned long)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
//#define SPI_MCR_ROOE_MASK                        0x1000000u
//#define SPI_MCR_ROOE_SHIFT                       24
//#define SPI_MCR_PCSSE_MASK                       0x2000000u
//#define SPI_MCR_PCSSE_SHIFT                      25
//#define SPI_MCR_MTFE_MASK                        0x4000000u
//#define SPI_MCR_MTFE_SHIFT                       26
//#define SPI_MCR_FRZ_MASK                         0x8000000u
//#define SPI_MCR_FRZ_SHIFT                        27
//#define SPI_MCR_DCONF_MASK                       0x30000000u
//#define SPI_MCR_DCONF_SHIFT                      28
////#define SPI_MCR_DCONF(x)                         (((unsigned long)(((unsigned long)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
//#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
//#define SPI_MCR_CONT_SCKE_SHIFT                  30
//#define SPI_MCR_MSTR_MASK                        0x80000000u
//#define SPI_MCR_MSTR_SHIFT                       31
///* TCR Bit Fields */
//#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
//#define SPI_TCR_SPI_TCNT_SHIFT                   16
////#define SPI_TCR_SPI_TCNT(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
///* CTAR Bit Fields */
//#define SPI_CTAR_BR_MASK                         0xFu
//#define SPI_CTAR_BR_SHIFT                        0
////#define SPI_CTAR_BR(x)                           (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
//#define SPI_CTAR_DT_MASK                         0xF0u
//#define SPI_CTAR_DT_SHIFT                        4
//#define SPI_CTAR_DT(x)                           (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
//#define SPI_CTAR_ASC_MASK                        0xF00u
//#define SPI_CTAR_ASC_SHIFT                       8
//#define SPI_CTAR_ASC(x)                          (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
//#define SPI_CTAR_CSSCK_MASK                      0xF000u
//#define SPI_CTAR_CSSCK_SHIFT                     12
//#define SPI_CTAR_CSSCK(x)                        (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
//#define SPI_CTAR_PBR_MASK                        0x30000u
//#define SPI_CTAR_PBR_SHIFT                       16
//#define SPI_CTAR_PBR(x)                          (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
//#define SPI_CTAR_PDT_MASK                        0xC0000u
//#define SPI_CTAR_PDT_SHIFT                       18
//#define SPI_CTAR_PDT(x)                          (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
//#define SPI_CTAR_PASC_MASK                       0x300000u
//#define SPI_CTAR_PASC_SHIFT                      20
//#define SPI_CTAR_PASC(x)                         (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
//#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
//#define SPI_CTAR_PCSSCK_SHIFT                    22
//#define SPI_CTAR_PCSSCK(x)                       (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
//#define SPI_CTAR_LSBFE_MASK                      0x1000000u
//#define SPI_CTAR_LSBFE_SHIFT                     24
//#define SPI_CTAR_CPHA_MASK                       0x2000000u
//#define SPI_CTAR_CPHA_SHIFT                      25
//#define SPI_CTAR_CPOL_MASK                       0x4000000u
//#define SPI_CTAR_CPOL_SHIFT                      26
//#define SPI_CTAR_FMSZ_MASK                       0x78000000u
//#define SPI_CTAR_FMSZ_SHIFT                      27
//#define SPI_CTAR_FMSZ(x)                         (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
//#define SPI_CTAR_DBR_MASK                        0x80000000u
//#define SPI_CTAR_DBR_SHIFT                       31
///* CTAR_SLAVE Bit Fields */
//#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
//#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
//#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
//#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
//#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
//#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
//#define SPI_CTAR_SLAVE_FMSZ(x)                   (((unsigned long)(((unsigned long)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
///* SR Bit Fields */
//#define SPI_SR_POPNXTPTR_MASK                    0xFu
//#define SPI_SR_POPNXTPTR_SHIFT                   0
//#define SPI_SR_POPNXTPTR(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
//#define SPI_SR_RXCTR_MASK                        0xF0u
//#define SPI_SR_RXCTR_SHIFT                       4
//#define SPI_SR_RXCTR(x)                          (((unsigned long)(((unsigned long)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
//#define SPI_SR_TXNXTPTR_MASK                     0xF00u
//#define SPI_SR_TXNXTPTR_SHIFT                    8
//#define SPI_SR_TXNXTPTR(x)                       (((unsigned long)(((unsigned long)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
//#define SPI_SR_TXCTR_MASK                        0xF000u
//#define SPI_SR_TXCTR_SHIFT                       12
//#define SPI_SR_TXCTR(x)                          (((unsigned long)(((unsigned long)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
//#define SPI_SR_RFDF_MASK                         0x20000u
//#define SPI_SR_RFDF_SHIFT                        17
//#define SPI_SR_RFOF_MASK                         0x80000u
//#define SPI_SR_RFOF_SHIFT                        19
//#define SPI_SR_TFFF_MASK                         0x2000000u
//#define SPI_SR_TFFF_SHIFT                        25
//#define SPI_SR_TFUF_MASK                         0x8000000u
//#define SPI_SR_TFUF_SHIFT                        27
//#define SPI_SR_EOQF_MASK                         0x10000000u
//#define SPI_SR_EOQF_SHIFT                        28
//#define SPI_SR_TXRXS_MASK                        0x40000000u
//#define SPI_SR_TXRXS_SHIFT                       30
//#define SPI_SR_TCF_MASK                          0x80000000u
//#define SPI_SR_TCF_SHIFT                         31
///* RSER Bit Fields */
//#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
//#define SPI_RSER_RFDF_DIRS_SHIFT                 16
//#define SPI_RSER_RFDF_RE_MASK                    0x20000u
//#define SPI_RSER_RFDF_RE_SHIFT                   17
//#define SPI_RSER_RFOF_RE_MASK                    0x80000u
//#define SPI_RSER_RFOF_RE_SHIFT                   19
//#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
//#define SPI_RSER_TFFF_DIRS_SHIFT                 24
//#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
//#define SPI_RSER_TFFF_RE_SHIFT                   25
//#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
//#define SPI_RSER_TFUF_RE_SHIFT                   27
//#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
//#define SPI_RSER_EOQF_RE_SHIFT                   28
//#define SPI_RSER_TCF_RE_MASK                     0x80000000u
//#define SPI_RSER_TCF_RE_SHIFT                    31
///* PUSHR Bit Fields */
//#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
//#define SPI_PUSHR_TXDATA_SHIFT                   0
//#define SPI_PUSHR_TXDATA(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
//#define SPI_PUSHR_PCS_MASK                       0x3F0000u
//#define SPI_PUSHR_PCS_SHIFT                      16
//#define SPI_PUSHR_PCS(x)                         (((unsigned long)(((unsigned long)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
//#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
//#define SPI_PUSHR_CTCNT_SHIFT                    26
//#define SPI_PUSHR_EOQ_MASK                       0x8000000u
//#define SPI_PUSHR_EOQ_SHIFT                      27
//#define SPI_PUSHR_CTAS_MASK                      0x70000000u
//#define SPI_PUSHR_CTAS_SHIFT                     28
//#define SPI_PUSHR_CTAS(x)                        (((unsigned long)(((unsigned long)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
//#define SPI_PUSHR_CONT_MASK                      0x80000000u
//#define SPI_PUSHR_CONT_SHIFT                     31
///* PUSHR_SLAVE Bit Fields */
//#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFFFFFu
//#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
//#define SPI_PUSHR_SLAVE_TXDATA(x)                (((unsigned long)(((unsigned long)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
///* POPR Bit Fields */
//#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
//#define SPI_POPR_RXDATA_SHIFT                    0
//#define SPI_POPR_RXDATA(x)                       (((unsigned long)(((unsigned long)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
///* TXFR0 Bit Fields */
//#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
//#define SPI_TXFR0_TXDATA_SHIFT                   0
//#define SPI_TXFR0_TXDATA(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
//#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
//#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
//#define SPI_TXFR0_TXCMD_TXDATA(x)                (((unsigned long)(((unsigned long)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
///* TXFR1 Bit Fields */
//#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
//#define SPI_TXFR1_TXDATA_SHIFT                   0
//#define SPI_TXFR1_TXDATA(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
//#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
//#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
//#define SPI_TXFR1_TXCMD_TXDATA(x)                (((unsigned long)(((unsigned long)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
///* TXFR2 Bit Fields */
//#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
//#define SPI_TXFR2_TXDATA_SHIFT                   0
//#define SPI_TXFR2_TXDATA(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
//#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
//#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
//#define SPI_TXFR2_TXCMD_TXDATA(x)                (((unsigned long)(((unsigned long)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
///* TXFR3 Bit Fields */
//#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
//#define SPI_TXFR3_TXDATA_SHIFT                   0
//#define SPI_TXFR3_TXDATA(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
//#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
//#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
//#define SPI_TXFR3_TXCMD_TXDATA(x)                (((unsigned long)(((unsigned long)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
///* RXFR0 Bit Fields */
//#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
//#define SPI_RXFR0_RXDATA_SHIFT                   0
//#define SPI_RXFR0_RXDATA(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
///* RXFR1 Bit Fields */
//#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
//#define SPI_RXFR1_RXDATA_SHIFT                   0
//#define SPI_RXFR1_RXDATA(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
///* RXFR2 Bit Fields */
//#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
//#define SPI_RXFR2_RXDATA_SHIFT                   0
//#define SPI_RXFR2_RXDATA(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
///* RXFR3 Bit Fields */
//#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
//#define SPI_RXFR3_RXDATA_SHIFT                   0
//#define SPI_RXFR3_RXDATA(x)                      (((unsigned long)(((unsigned long)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
//
///**
// * @}
// */ /* end of group SPI_Register_Masks */
//
//
///* SPI - Peripheral instance base addresses */
///** Peripheral SPI0 base pointer */
//#define SPI0_BASE_PTR                            ((SPI_MemMapPtr)0x4002C000u)
///** Peripheral SPI1 base pointer */
//#define SPI1_BASE_PTR                            ((SPI_MemMapPtr)0x4002D000u)
///** Peripheral SPI2 base pointer */
//#define SPI2_BASE_PTR                            ((SPI_MemMapPtr)0x400AC000u)
//
///* ----------------------------------------------------------------------------
//   -- SPI - Register accessor macros
//   ---------------------------------------------------------------------------- */
//
///**
// * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
// * @{
// */
//
//
///* SPI - Register instance definitions */
///* SPI0 */
//#define SPI0_MCR                                 SPI_MCR_REG(SPI0_BASE_PTR)
//#define SPI0_TCR                                 SPI_TCR_REG(SPI0_BASE_PTR)
//#define SPI0_CTAR0                               SPI_CTAR_REG(SPI0_BASE_PTR,0)
//#define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0_BASE_PTR,0)
//#define SPI0_CTAR1                               SPI_CTAR_REG(SPI0_BASE_PTR,1)
//#define SPI0_SR                                  SPI_SR_REG(SPI0_BASE_PTR)
//#define SPI0_RSER                                SPI_RSER_REG(SPI0_BASE_PTR)
//#define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0_BASE_PTR)
//#define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0_BASE_PTR)
//#define SPI0_POPR                                SPI_POPR_REG(SPI0_BASE_PTR)
//#define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0_BASE_PTR)
//#define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0_BASE_PTR)
//#define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0_BASE_PTR)
//#define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0_BASE_PTR)
//#define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0_BASE_PTR)
//#define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0_BASE_PTR)
//#define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0_BASE_PTR)
//#define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0_BASE_PTR)
///* SPI1 */
//#define SPI1_MCR                                 SPI_MCR_REG(SPI1_BASE_PTR)
//#define SPI1_TCR                                 SPI_TCR_REG(SPI1_BASE_PTR)
//#define SPI1_CTAR0                               SPI_CTAR_REG(SPI1_BASE_PTR,0)
//#define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1_BASE_PTR,0)
//#define SPI1_CTAR1                               SPI_CTAR_REG(SPI1_BASE_PTR,1)
//#define SPI1_SR                                  SPI_SR_REG(SPI1_BASE_PTR)
//#define SPI1_RSER                                SPI_RSER_REG(SPI1_BASE_PTR)
//#define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1_BASE_PTR)
//#define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1_BASE_PTR)
//#define SPI1_POPR                                SPI_POPR_REG(SPI1_BASE_PTR)
//#define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1_BASE_PTR)
//#define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1_BASE_PTR)
//#define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1_BASE_PTR)
//#define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1_BASE_PTR)
//#define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1_BASE_PTR)
//#define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1_BASE_PTR)
//#define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1_BASE_PTR)
//#define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1_BASE_PTR)
///* SPI2 */
//#define SPI2_MCR                                 SPI_MCR_REG(SPI2_BASE_PTR)
//#define SPI2_TCR                                 SPI_TCR_REG(SPI2_BASE_PTR)
//#define SPI2_CTAR0                               SPI_CTAR_REG(SPI2_BASE_PTR,0)
//#define SPI2_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI2_BASE_PTR,0)
//#define SPI2_CTAR1                               SPI_CTAR_REG(SPI2_BASE_PTR,1)
//#define SPI2_SR                                  SPI_SR_REG(SPI2_BASE_PTR)
//#define SPI2_RSER                                SPI_RSER_REG(SPI2_BASE_PTR)
//#define SPI2_PUSHR                               SPI_PUSHR_REG(SPI2_BASE_PTR)
//#define SPI2_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI2_BASE_PTR)
//#define SPI2_POPR                                SPI_POPR_REG(SPI2_BASE_PTR)
//#define SPI2_TXFR0                               SPI_TXFR0_REG(SPI2_BASE_PTR)
//#define SPI2_TXFR1                               SPI_TXFR1_REG(SPI2_BASE_PTR)
//#define SPI2_TXFR2                               SPI_TXFR2_REG(SPI2_BASE_PTR)
//#define SPI2_TXFR3                               SPI_TXFR3_REG(SPI2_BASE_PTR)
//#define SPI2_RXFR0                               SPI_RXFR0_REG(SPI2_BASE_PTR)
//#define SPI2_RXFR1                               SPI_RXFR1_REG(SPI2_BASE_PTR)
//#define SPI2_RXFR2                               SPI_RXFR2_REG(SPI2_BASE_PTR)
//#define SPI2_RXFR3                               SPI_RXFR3_REG(SPI2_BASE_PTR)
//
///* SPI - Register array accessors */
//#define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0_BASE_PTR,index2)
//#define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1_BASE_PTR,index2)
//#define SPI2_CTAR(index2)                        SPI_CTAR_REG(SPI2_BASE_PTR,index2)
//#define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0_BASE_PTR,index2)
//#define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1_BASE_PTR,index2)
//#define SPI2_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI2_BASE_PTR,index2)
//
///**
// * @}
// */ /* end of group SPI_Register_Accessor_Macros */
//
//
///**
// * @}
// */ /* end of group SPI_Peripheral */

//*****************************************************************************
//
// The rate of the SSI clock and derived values.
//
//*****************************************************************************
#define SSI_CLK_RATE            10000000
#define SSI_CLKS_PER_MS         (SSI_CLK_RATE / 1000)
#define STATUS_READS_PER_MS     (SSI_CLKS_PER_MS / 16)

//*****************************************************************************
//
// Labels for the instructions supported by the Winbond part.
//
//*****************************************************************************
#define INSTR_WRITE_ENABLE      0x06
#define INSTR_WRITE_DISABLE     0x04
#define INSTR_READ_STATUS       0x05
#define INSTR_WRITE_STATUS      0x01
#define INSTR_READ_DATA         0x03
#define INSTR_FAST_READ         0x0B
#define INSTR_PAGE_PROGRAM      0x02
#define INSTR_BLOCK_ERASE       0xD8
#define INSTR_SECTOR_ERASE      0x20
#define INSTR_CHIP_ERASE        0xC7
#define INSTR_POWER_DOWN        0xB9
#define INSTR_POWER_UP          0xAB
#define INSTR_MAN_DEV_ID        0x90
#define INSTR_JEDEC_ID          0x9F

//*****************************************************************************
//
// Status register bit definitions
//
//*****************************************************************************
#define STATUS_BUSY                 0x01
#define STATUS_WRITE_ENABLE_LATCH   0x02
#define STATUS_BLOCK_PROTECT_0      0x04
#define STATUS_BLOCK_PROTECT_1      0x08
#define STATUS_BLOCK_PROTECT_2      0x10
#define STATUS_TOP_BOTTON_WP        0x20
#define STATUS_REGISTER_PROTECT     0x80

//*****************************************************************************
//
// Manufacturer and device IDs that we expect to see.
//
//*****************************************************************************
#define MANUFACTURER_WINBOND    0xEF
#define DEVICE_ID_W25X80A       0x13
#define DEVICE_ID_W25X16        0x14

//*****************************************************************************
//
// Block, sector, page and chip sizes for the supported device.  Some of the
// code here assumes (reasonably) that these are all powers of two.
//
//*****************************************************************************
#define W25X80A_BLOCK_SIZE      (64 * 1024)
#define W25X80A_SECTOR_SIZE     (4 * 1024)
#define W25X80A_PAGE_SIZE       256
#define W25X80A_CHIP_SIZE       (1024 * 1024)

#define W25X16_BLOCK_SIZE      (64 * 1024)
#define W25X16_SECTOR_SIZE     (4 * 1024)
#define W25X16_PAGE_SIZE       256
#define W25X16_CHIP_SIZE       (2 * 1024 * 1024)

//*****************************************************************************
//
// The number of times we query the device status waiting for it to be idle
// after various operations have taken place and during initialization.
//
//*****************************************************************************
#define MAX_BUSY_POLL_IDLE              100
#define MAX_BUSY_POLL_ERASE_SECTOR      (STATUS_READS_PER_MS * 250)
#define MAX_BUSY_POLL_ERASE_BLOCK       (STATUS_READS_PER_MS * 1000)
#define MAX_BUSY_POLL_ERASE_CHIP        (STATUS_READS_PER_MS * 10000)
#define MAX_BUSY_POLL_PROGRAM_PAGE      (STATUS_READS_PER_MS * 3)


extern void SPIEnable(SPI_MemMapPtr port);
extern void SPIDisable(SPI_MemMapPtr port);
extern void SPIConfiguration(SPI_MemMapPtr port, tBoolean bHost);
extern void SPIDataPut(SPI_MemMapPtr port, unsigned char ucData, tBoolean bState);
extern void SPIDataGet(SPI_MemMapPtr port, unsigned char *ucData, tBoolean bState);
extern tBoolean SPIFlashInit(void);
extern tBoolean SPIFlashIdleWait(unsigned long ulMaxRetries);
extern tBoolean SPIFlashIDGet(unsigned char *pucManufacturer, unsigned char *pucDevice);
extern tBoolean SPIFlashIsBusy(void);
extern unsigned long SPIFlashWrite(unsigned long ulAddress, unsigned long ulLength,
		unsigned char *pucSrc);
extern unsigned long SPIFlashRead(unsigned long ulAddress, unsigned long ulLength,
		unsigned char *pucDst);
static unsigned char SPIFlashStatusGet(void);
static void SPIFlashInstructionWrite(unsigned char ucInstruction,
		unsigned char *ucData, unsigned short usLen);
static void SPIFlashInstructionRead(unsigned char *ucData, unsigned long ulLen);
static void SPIFlashInstructionDataWrite(unsigned char *ucData,
		unsigned short usLen);
static tBoolean SPIFlashWriteEnable(void);

#endif//__SPI_H__

